Conference Description
Key Takeaways
- DAC 2026 (Design Automation Conference) takes place July 26–29, 2026, at the Long Beach Convention Center in California
- The 63rd edition reports record submission numbers, with a 26.34% increase in Research Track submissions and 26% growth in Engineering Track submissions
- Artificial intelligence dominates the programme, with 55% of content covering AI and design topics
- Core technical tracks span AI, design, electronic design automation (EDA), hardware security, and systems engineering
- Keynote speakers include 2025 Nobel Laureate in Physics John Martinis (Qolab) and Dr. Baaziz Achour (Qualcomm Technologies)
- Sponsored by ACM SIGDA, IEEE, and the IEEE Council on Electronic Design Automation (CEDA)
Introduction
The Design Automation Conference returns for its 63rd edition in July 2026, bringing together the global electronic design automation community at a moment when artificial intelligence is fundamentally reshaping how chips and systems are conceived, verified, and manufactured. DAC 2026 arrives as semiconductor companies face mounting pressure to accelerate design cycles while managing unprecedented complexity in advanced process nodes, heterogeneous integration, and security requirements.
This year’s conference reports record-breaking submission numbers across both its Research and Engineering tracks, reflecting intensified industry and academic interest in the intersection of machine learning and hardware design. The programme’s heavy emphasis on AI—comprising more than half of all sessions—signals a maturation point where generative models and intelligent automation have moved from experimental curiosity to production necessity in EDA workflows.
About the Design Automation Conference
DAC serves as the primary annual gathering for professionals working across the semiconductor design ecosystem, from individual chip components through complete system architectures. The conference operates under the joint sponsorship of the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE), with additional support from ACM’s Special Interest Group on Design Automation (SIGDA) and IEEE’s Council on Electronic Design Automation (CEDA). The IEEE Solid-State Circuits Society provides technical conference sponsorship.
The four-day event encompasses hundreds of sessions distributed across workshops, tutorials, technical presentations, keynote addresses, and an exhibition hall featuring EDA tool vendors and technology providers. Sunday programming focuses on intensive workshops and tutorials designed to provide deep technical training before the main conference sessions begin.
Technical Programme Structure
DAC 2026 organises its content around five interconnected pillars: AI, Design, EDA, Security, and Systems. This structure reflects the reality that modern semiconductor development requires expertise spanning multiple disciplines simultaneously. A verification engineer working on an advanced system-on-chip must understand not only traditional design rule checking but also how machine learning can accelerate coverage closure, how chiplet-based architectures affect verification strategies, and how hardware security vulnerabilities might be introduced during the design process.
The Research Track showcases peer-reviewed academic work pushing the boundaries of design automation theory and methodology. The 26.34% increase in submissions suggests growing research investment in areas such as quantum computing applications to EDA, novel approaches to AI-assisted synthesis, and formal methods for security verification. The Engineering Track, which saw 26% submission growth, provides a complementary practitioner perspective where designers share real-world implementation experiences, challenges encountered in production environments, and solutions developed through hands-on engineering.
Artificial Intelligence as a Central Theme
The prominence of AI throughout DAC 2026—with 55% of the programme dedicated to AI and design topics—reflects a fundamental shift in how the semiconductor industry approaches automation. Traditional EDA tools relied on deterministic algorithms and heuristics refined over decades. The current generation of tools increasingly incorporates machine learning for tasks ranging from placement and routing optimisation to design space exploration and verification closure prediction.
Several TechTalk speakers represent organisations at the forefront of this transformation. Bronco AI and ChipAgents.ai, both platinum industry partners, are developing AI-native approaches to chip design workflows. NVIDIA’s presence through speakers addressing semiconductor and EDA applications underscores how companies with deep AI expertise are applying those capabilities to accelerate their own silicon development while creating tools for the broader industry.
The ICLAD Hackathon provides a competitive venue for teams to demonstrate generative AI capabilities in chip design, offering a practical testbed for emerging techniques that may eventually find their way into commercial EDA tools.
Keynote and Featured Speakers
The keynote programme brings together perspectives from quantum computing, mobile semiconductors, and academic research. John Martinis, CTO and Co-Founder of Qolab and recipient of the 2025 Nobel Prize in Physics, represents the quantum computing frontier where design automation faces entirely new challenges in qubit control, error correction, and system integration. Dr. Baaziz Achour, Executive Vice President and Chief Technology Officer at Qualcomm Technologies, offers insight from a company shipping billions of advanced processors annually across mobile, automotive, and IoT applications. Jan M. Rabaey, Professor Emeritus at the University of California at Berkeley, provides academic perspective on the evolution of digital design methodologies.
Timothy Costa, General Manager and Vice President of Computational Engineering at NVIDIA, delivers the Sunday Welcome Address, setting context for the week’s technical discussions. SkyTalk sessions feature senior technology leaders from Intel, IBM Research, and Microsoft, each addressing challenges in semiconductor research and development, AI silicon engineering, and global manufacturing operations.
Analyst Reviews from Jay Vleeschhouwer of Griffin Securities and Dylan Patel of SemiAnalysis provide market and industry analysis, helping attendees understand commercial dynamics shaping EDA investment and semiconductor design trends.
Hardware Security and Emerging Architectures
Security has evolved from a peripheral concern to a core design requirement as chips increasingly handle sensitive data and critical infrastructure functions. DAC’s dedicated security track addresses vulnerabilities that can be introduced at various stages of the design and manufacturing process, from malicious logic insertion to side-channel leakage. Hack@DAC, described as the world’s largest hardware security competition, provides a hands-on environment where participants identify and exploit vulnerabilities in realistic designs.
The systems track addresses the growing complexity of heterogeneous integration, where chiplets from multiple vendors and process technologies must interoperate within a single package. This architectural shift creates new challenges for design automation tools that historically assumed monolithic die designs. Verification, thermal analysis, and signal integrity all require rethinking when designs span multiple silicon components connected through advanced packaging technologies.
Academic and Student Programmes
DAC maintains strong connections to academic research through several dedicated programmes. The Ph.D. Forum provides a premier venue for doctoral students to present their research and receive feedback from industry and academic experts. The DAC Young Fellows programme supports advanced EDA students, while the University Demonstration at DAC (UD@DAC), now in its 36th year, allows university researchers to showcase EDA projects in development.
The Poster Gladiator competition offers daily sessions where researchers defend their work in a competitive format, encouraging clear communication of complex technical concepts. These programmes serve a workforce development function critical to an industry facing persistent talent shortages in specialised design automation roles.
Industry Partnership and Exhibition
The exhibition hall features the major EDA vendors alongside emerging companies developing AI-native design tools. Platinum industry partners include Bronco AI, ChipAgents.ai, and Siemens. Silver partners encompass established players such as Cadence, Synopsys, and Keysight alongside newer entrants including Architect Labs and Ricursive. Amazon’s Kuiper division and Verifaix participate at the bronze level, while VoltAI holds gold partnership status.
This mix of established EDA companies and AI-focused startups reflects the competitive dynamics reshaping the industry, where traditional tool vendors are integrating machine learning capabilities while new entrants attempt to reimagine design workflows from first principles.
Who Should Attend
DAC 2026 serves engineers and designers working directly on chip and system implementation, researchers advancing design automation methodologies, and technology executives responsible for EDA tool selection and design flow strategy. The Engineering Track specifically targets practitioners seeking real-world implementation guidance, while the Research Track appeals to those developing next-generation techniques. Students and academics benefit from dedicated programmes, networking opportunities, and exposure to industry challenges that can inform research directions.